Product Summary

The HY57V1616100TC-6 is 16,777,216-bits CMOS Synchronous DRAM, ideally suited for the main memory and graphic applications which require large memory density and high bandwidth. It is organized as 2banks of 524,288x16. HY57V1616100TC-6 is offering fully synchronous operation referenced to a positive edge clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.

Parametrics

HY57V1616100TC-6 absolute maximum ratings: (1)Ambient Temperature: 0 ~ 70 ℃; (2)Storage Temperature: -55 ~ 125 ℃; (3)Voltage on Any Pin relative to VSS: -1.0 ~ 4.6 V; (4)Voltage on VDD relative to VSS: -1.0 ~ 4.6 V; (5)Short Circuit Output Current: 50 mA; (6)Power Dissipation: 1 W; (7)Soldering Temperature: 260℃,Sec.

Features

HY57V1616100TC-6 features: (1)Single 3.0V to 3.6V power supply; (2)All device pins are compatible with LVTTL interface; (3)JEDEC standard 400mil 50pin TSOP-II with 0.8mm of pin pitch; (4)All inputs and outputs referenced to positive edge of system clock; (5)Data mask function by UDQM/LDQM; (6)Internal two banks operation; (7)Auto refresh and self refresh; (8)4096 refresh cycles / 64ms; (9)Programmable Burst Length and Burst Type.

Diagrams

HY57V1616100TC-6 functional block diagram

HY57V121620(L)T
HY57V121620(L)T
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Negotiable 
HY57V161610D
HY57V161610D
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Negotiable 
HY57V161610D-I
HY57V161610D-I
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Negotiable 
HY57V161610E
HY57V161610E
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Negotiable 
HY57V161610ET-I
HY57V161610ET-I
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Negotiable 
HY57V161610ETP-I
HY57V161610ETP-I
Other

Data Sheet
Negotiable